Since the development of transistors and integrated circuits, there have been technology advances aimed at reducing device size, both vertically and laterally, and to increase device density and speed. In constructing a bipolar transistor having a traditional configuration, the minimum size of the emitter contact has been determined by the photolithographic limit in producing the narrowest line. This line corresponds to the width of the emitter contact.
The size of the base-collector junctions has been determined by the process ability to reregister another set of lines to define the base contacts. The minimum size of the emitter is wider than the width of the emitter contact resulting in the minimum size of the base-collector junction being greater than the width of three contact lines plus two spaces. Since the space width generally equals the line width, this results in a base-collector junction in the order of five times the width of the emitter junction.
A self-aligned emitter process which is specific to silicon technology has been used to reduce those dimensions. In this process, both the emitter and the base contacts are determined by one mask. The emitter mask opening defining the emitter size is determined by a lithography step, but the mask opening is reduced by the thickness of an oxidized layer of poly-silicon to yield a smaller opening for the emitter contact. This process is limited to silicon technology and cannot be applied to gallium arsenide or other technologies since it requires a thermal oxidation step to passivate a poly-silicon base contact from the emitter. This thermal oxidation step is not compatible with gallium arsenide technology.